ASIC Implementation of Pezaris Multiplier in DIT FFT Architectures | DealShopping Deutschland
  1. Home
  2. ASIC Implementation of Pezaris Multiplier in DIT FFT Architectures
  • #

ASIC Implementation of Pezaris Multiplier in DIT FFT Architectures

39.90 EUR

Teilen:

Ähnliche Produkte

Efficient Hardware Implementation of an Advanced Turbo Decoder

Efficient Hardware Implementation of an Advanced Turbo Decoder

49.00 EUR
Low Power Reversible Logic FP-AU ASIC

Low Power Reversible Logic FP-AU ASIC

35.90 EUR
RSA Cryptosystem: Asic implementation using cadence

RSA Cryptosystem: Asic implementation using cadence

49.00 EUR
Digital PLL for Audio Applications: Based on ASIC Low Power and FPGA flow

Digital PLL for Audio Applications: Based on ASIC Low Power and FPGA flow

49.00 EUR
ASIC Design for a Coherent Optical Receiver DSPU: Design issues related to high-speed MOS ASIC for a coherent optical QPSK with polarization multiplex receiver DSPU

ASIC Design for a Coherent Optical Receiver DSPU: Design issues related to high-speed MOS ASIC for a coherent optical QPSK with polarization multiplex receiver DSPU

49.00 EUR
Design Methodology for highly Reliable Digital ASIC Designs: Applied to Network-Centric System Middleware Switch Processor

Design Methodology for highly Reliable Digital ASIC Designs: Applied to Network-Centric System Middleware Switch Processor

69.90 EUR