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Design for Yield and Reliability for Nanometer CMOS Digital Circuits

59.90 EUR

Dieses Buch liefert praxisnahe Techniken zur Optimierung von Yield und Zuverlässigkeit bei Nanometer-CMOS-Digitalschaltungen, behandelt statistische Entwurfsansätze, Soft‑Error‑Simulationen sowie adaptive Body‑Bias‑Strategien und negative Kapazitätskreise.

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