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Logic Synthesis and SOC Prototyping: RTL Design using VHDL

118.00 EUR 106.99 EUR 9% Off

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Logic Synthesis and SOC Prototyping: RTL Design using VHDL

Medimops DE
106.99 EUR
29-07-2026 06:23:56
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Logic Synthesis and SOC Prototyping

SpringerLink DE
118.00 EUR
29-07-2026 09:03:59

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